Review by Paul Hulme
Overview of an analysis of Transmeta's Crusoe Processor
Statement of intent
It is my role in this project to do an unbiased analysis of Transmeta's Crusoe processor with minimal conclusions about how it matches up to other processors. This will enable Michael Hughes to have a useful source of information to use when the time comes for him to draw detailed conclusions about how Apple's G4 stacks up compared to the Crusoe. It may also be useful in itself as a study of the Architecture. At this time I know very little of the Transmeta Crusoe processor, other than it's basic design goals:
- x86 compatibility
- low power consumption
- adequate performance for everyday user applications
- to be the first microprocessor targeted at the mobile computing market
To do this Transmeta will need to create a very efficient processor that will be able to beat the current competition in terms of performance and power consumption.
The Instruction Set
An attempt will be made to find what paradigm the Crusoe's Instruction Set (I.S) most closely matches, i.e. RISC (Reduced Instruction Set Computer) or CISC (Complex Instruction Set Computer). I will also investigate any specialised instructions that Transmeta have decided to include in the I.S and their associated functions *.
* This will obviously be limited (as will much of this analysis) by whatever information is available on this topic, as detailed information about the processor has not yet been made available.
Motherboard/Interface support
The memory hierarchy proposed in the motherboards that will support the Transmeta Crusoe processor will be assessed. The size of cache that will typically be implemented (and the peripherals that will be supported) in systems that are based around the Crusoe Central Processing Unit (CPU) will be determined. An attempt will also be made at finding valid benchmarks for the proposed cache and input/output (I/O) interface.
Architecture
In this section the data path of the Crusoe will be investigated. Specifically: my initial reactions about this CPU were that the amount of effort used in translating Intel instructions into the Crusoe's native instructions would be very large and so may make it inefficient in comparison to the Crusoe running it's own native instructions. The issue of backward (and upward) compatibility will also be evaluated, as this is a major issue if the Crusoe intends to perform well in its target market.
A major issue when investigating the Architecture of the Crusoe CPU is its pipeline. Pipelining is a modern technique used to improve the throughput of a CPU: I expect the Crusoe processor to use a pipelined implementation. There are issues associated with the use of a pipeline: for example, the use of variable instruction lengths and/or variable instruction run-times can adversely affect the performance of a pipelined CPU. The Crusoe processor may have some issues in this area because it's native instructions have an instruction length of 128bits but the software it will be targeted at (windows9x / millennium particularly) expect an instruction length of 32bits.
Benchmarking
This section is concerned with the Benchmarking of the Crusoe CPU. The benchmark statistics will probably only be from Transmeta itself and as such they probably cannot be taken at face value. With this in mind I will attempt to scrutinise the benchmarking software that was used, in order to gain a clearer picture of actual performance.
