G4 Instruction

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Instruction Set Used In The G4

As mentioned previously the G4 is a member of the PowerPC family of processors. This means that the G4 is a reduced instruction set computer (RISC). As the G4 processor is a 32-bit processor, all its instructions are 32-bit, and are generally of a fixed format, as shown.

Part Of The G4s Instruction Set Listings

This instruction set incorporates all of the standard instructions such as ADD, AND, COMPARE, LOAD, STORE, OR, SUBTRACT, as well as all of the various subordinate operations that you would expect to find in a processor. However as you would expect some of the mnemonics used for the instructions are not obvious, this can be put down to the fact that every microprocessor company has their own standard way of implementing and doing certain things. The main advance made in this processor as previously mentioned is the Velocity Engine (or Altivec Technology), which extends the instruction set architecture (ISA) of the PowerPC with the Velocity Engine instructions. The Velocity Engine instruction set provides 162 new instructions to speed up mainly computations, saying that none of the instructions allow significantly different functionality with the exception of load/store. All that has really been done is that the current instructions have been extended to incorporate 128-bit vector processing technology. However saying that, these advances allow significant differences in both instruction/data processing and performance of the processor as a unit. The Velocity Engine instructions are primarily user-level and can more easily be described by grouping them together into categories, and explaining each category, as bellow.

Vector integer arithmetic instructions
These instructions include arithmetic, logical, compare, rotate, and shift instructions. These are basic arithmetic and instructions implemented for 128-bit or less data.
Vector floating-point arithmetic instructions
These instructions again arithmetic, logical, etc instructions for floating point data. As before these are simply an adaptation of previous instructions to 128-bit or less data.
Vector load and store instructions
These are 128-bit instructions for loading, handling, manipulating and storing data.
Vector permutation and formatting instructions
These include pack, unpack, merge, splat, permute, select, and shift instructions.
Processor control instructions
These instructions are used to read and write from the vector status and control register (VSCR).
Memory control instructions
These instructions are used for managing caches.

These Velocity Engine instructions have been implemented by incorporating new registers and modifying old registers in the standard G4 (MPC7400) architecture. These new and changed registers include changes to the condition register, additions to the machine state as well as the implementation of new vector registers (VRs) used as source and destination registers for vector operations, and a vector status and control register (VSCR). However it’s not just new registers that have been implemented, two new operational modes have also been incorporated into the processor; these are Non-Java mode and Java mode. The differences being the operations that are carried out in each state while instructions or data is being processed.

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Last updated: January 30, 2001.